1. Field of the Invention
The present invention relates to a timing error detection circuit for detecting a timing error of symbols in a signal, a demodulation circuit for reproducing a symbol timing based on the detected timing error and methods thereof.
2. Description of the Related Art
In a radio communication system, modulation for putting a signal (information) on a carrier is performed on a sending side and demodulation for taking out the signal on the carrier is performed on a receiving side.
Among a variety of modulation methods, there is a phase shift keying (PSK) modulation as a format used for example for satellite broadcasting.
A modulation signal S(t) subjected to the PSK modulation is expressed by a formula (1) below.S(t)=exp(jθ(t))·exp(jωt)  (1)
In the above formula (1), θ(t) indicates a signal (information) converted to a phase and ω indicates a carrier frequency.
In a receiving apparatus, θ(t) is taken out from a modulation signal S(t) and subjected to demodulation for converting into a signal with meaning.
FIG. 10 is a view of the configuration of a demodulation circuit 100 in the receiving apparatus.
As shown in FIG. 10, the demodulation circuit 100 comprises a symbol timing reproduction circuit 101, a carrier reproduction circuit 102 and a symbol decode circuit 103.
The symbol timing reproduction circuit 101 is also called a clock reproduction circuit and used for correctly sampling data by an assumed clock in the demodulation circuit. Generally, a block generating a clock is not capable of generating a clock signal of strictly absolute cycle due to various factors. Therefore, it is necessary to detect a difference of the clock presumed in advance and an actual clock and to generate an accurate clock by feeding-back. The symbol timing reproduction circuit 101 corresponds to the feedback circuit.
The symbol timing reproduction circuit 101 carries out clock reproduction of a receiving signal S100 and outputs the result as a signal S101 to the carrier reproduction circuit 102.
A variety of circuits have been proposed as the symbol timing circuit 101 as such.
For example, the Japanese Unexamined Patent Publication No. 9-28597 discloses a symbol timing reproduction circuit capable of generating a phase signal and having high resistence against residual carrier by using the phase signal.
The carrier reproduction circuit 102 performs processing of removing carrier components from the signal S101.
Namely, the carrier reproduction circuit 102 performs canceling/erasing exp(jωt) as carrier components in the above formula (1) from the signal S101. Specifically, the carrier reproduction circuit 102 multiplies the signal S101 with a signal indicating exp(−jωt).
The symbol decode circuit 103 receives as an input the signal S102 corresponding to exp(jθ(t)) shown in the above formula (1) from the carrier reproduction circuit 102 and performs decode processing for converting by using a correspondence table of θ and the data.
However, in the symbol timing reproduction circuit disclosed in the above Japanese Unexamined Patent Publication No. 9-28597, since it is necessary to generate a phase signal, a ROM table for generating a phase signal, etc. has to be prepared, thus, there is a disadvantage that the circuit becomes complex and large in scale.